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| SCG4501 Synchronous Clock Generators PLL 2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com Features * 32 ppm Capture/Pull-In Range * Phase Locked Output Frequency Control * Intrinsically Low Jitter Crystal Oscillator * LVPECL Outputs with Disable Function * Dual Input References * LOR & LOL combined alarm output * Force Free Run Function * Automatic Free Run operation on loss of both References A & B * Input Duty Cycle Tolerant Bulletin Page Revision Date Issued By SG040 1 of 16 P01 13 NOV 03 MBatts * 3.3V dc Power Supply * Small Size: 1 Square Inch General Description The SCG4501 is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4501 can lock to one of two external references, which is selectable using the SELAB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4501 includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FRstatus pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to 20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1" x 1.025" x .45" on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180C surface mount reflow processes. Maximum Dimension Package Outline Figure 1 Block Diagram Figure 2 10 k FORCE FREE RUN 33 FREE RUN STATUS 10 k ALARM Q QN REFA REFB 33 8 KHz PHASE ALIGNER DPFD ANALOG FILTER LOW JITTER VCXO SEL AB 10 k 1/N 33 ENABLE/ TRI-STATE 10 k OPTIONAL REFERENCE OUTPUT Absolute Maximum Rating Table 1 Symbol Vcc Vi Ts Parameter Power Supply Voltage Input Voltage Storage Temperature Minimum -0.5 -0.5 -65.0 Nominal Maximum +4.0 +5.5 +100 Units Volts Volts C Notes 1.0 1.0 1.0 Preliminary Data Sheet #: SG040 Page 2 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Operating Specifications Table 2 Symbol Vcc Icc To Ffr Fcap Fbw Tjtol Taq Parameter Power Supply Voltage Power Supply Current Temperature Range Free Run Frequency Capture/pull-in range Jitter Filter Bandwidth Input Jitter Tolerance (Input Jitter Frequencies 10 Hz) Minimum 3.135 170 0 -20 -32 31.25 1 Nominal 3.3 230 - Maximum 3.465 280 70 20 32 10 - Units Volts mA C ppm ppm Hz s s Notes 2.0 4.0 3.0 8 kHz Ref. units 19.44 MHz Ref. units Typical Acquisition Time Data Acquisition from a cold power-up: Phase lock within 12ns: 50 sec Phase lock settled: 220 sec Alarm time: <1.5 sec Acquisition from Free Run: Phase lock within 12ns: 50 sec Phase lock settled: 220 sec Alarm time: Typically no alarm Frequency lock with a 20PPM reference frequency step: Typically 0.5s. Phase lock during a switch between equal frequency references: Typically 0.5s, no alarm should be issued Trf DC MTIEsr Output Rise and Fall Time (20% 80%) Output Duty Cycle MTIE at Synchronization Rearrangement Dynamic Offset Range (0- 25) Dynamic Offset Range (25- 70) -50 -50 100 40 225 50 350 60 50 50 ps % 5.0, 6.0 ns ns 4.0 GR-253-CORE.1999 R5-136 Output Jitter Specifications Table 3 Frequency (MHz) 77.76 125.00 155.52 Jitter BW 10 Hz - 1 MHz pS (RMS) m UI 10 Typ. 10 Typ. 10 Typ. 0.776 Typ. 1.250 Typ. 1.556 Typ. SONET Jitter BW 12 kHz - 20 MHz pS (RMS) m UI 1 Max. 1 Max. 1 Max. 0.076 Max. 0.125 Max. 0.156 Max. NOTES: 1.0 Operation of the device at these or any other condition beyond those listed under Operating Specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. 2.0 Requires external regulation and supply decoupling. (22 uF, 330 pF) 3.0 3db loop response. 4.0 50-ohm load biased to 1.3 volts. 5.0 Entry into Free Run doesn't meet requirement for initial 2.33 seconds of self-timing. 6.0 If the selected reference is removed system response to the ALARM must be less than 10s. Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 3 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Input And Output Characteristics Table 4 Symbol Parameter Minimum 2.0 0.0 2.4 12.5 2.27 1.49 Nominal 2.34 1.51 50 Maximum 5.5 0.8 10 10 0.4 2.52 1.68 10 Units V V ns pF V V ns V V pF ps Notes CMOS Input and Output Characteristics Vih High Level Input Voltage Vil Tio Cl Voh Vol Tir Low Level Input Voltage I/O to Output Valid Output Capacitance High Level Output Voltage Low Level Output Voltage Input Reference Pulse Width PECL Output Characteristics Voh High Level PECL Voltage Vol Cl Tskew Low Level PECL Voltage Output Capacitance Differential Output Skew Input Selection / Output Response Table 5 RESET 1 X 0 0 0 0 0 0 0 0 ENABLE 0 1 0 0 0 0 0 0 0 0 SELAB X X X 0 1 0 1 1 0 X INPUTS REFA X X X A A NA NA A A NA REFB X X X A A A A NA NA NA FR X X 1 0 0 0 0 0 0 0 FRstatus 1 X 1 0 0 0 0 0 0 1 OUTPUTS ALARM X X X 0 0 1 0 1 0 1 NOTE Q X 0 X X X X X X X X QN X 1 X X X X X X X X FR RA RB U RB U RA FR FR NOTES: A Active FR Free Run Mode NA Not Active RA Locked to Reference A RB Locked to Reference B U Unstable (due to conditions shown, switch to active reference or Free Run) X Don't care Preliminary Data Sheet #: SG040 Page 4 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Typical MTIE Measurement Figure 3 Typical TDEV Measurement Figure 4 Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 5 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Typical MTIE at Synchronization Rearrangement. Reference B Equal to Inverse of Reference A, No Modulation. Figure 5 Preliminary Data Sheet #: SG040 Page 6 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Pin Description Table 6 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin Name ENABLE/TRI-STATE TCK TDO REFA SELAB RESET REFB Vee FRstatus Vcc N/C ALARM FR TDI TMS QN Vee Q Pin Information VCXO Enable. (Enable = 0, Disable = 1 = CMOS Outputs Tri-stated) No Connection, Internal Factory Programming Input. No Connection, Internal Factory Programming Input. CMOS Reference Frequency Input. Input Reference Select Pin. (REFA = 0, REFB = 1) RESET. (RESET = 1) CMOS Reference Frequency Input. Ground. Free Run Status. (FR = 1) Supply Voltage relative to ground. No Connection. (Optional Reference Output Available) Loss of Reference / Lock alarm. (Alarm = 1) Force Free Run. (Phase Lock = 0, Free Run = 1) No Connection, Internal Factory Programming Input. No Connection, Internal Factory Programming Input. LVPECL Complementary Output. Ground. LVPECL Output. 9.0 8.0 8.0 8.0, 8.1 9.0 9.0 Note 9.0 8.0 8.0 NOTES 8.0 Do not connect pin 8.1 Contact a Sales Representative for availibilty and use of optional reference output 9.0 Input pulled to ground Circuit Board Footprint & Keepout Recommendations Figure 6 0.8650 [21.97 mm] 0.0650 [1.65 mm] 1.0400 [26.42 mm] 0.8400 [21.34 mm] Keep Out Area 0.1000 [2.54 mm] 0.1000 [2.54 mm] 0.0350 [0.89 mm] 1.0700 [27.18 mm] Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 7 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Loss of Reference Condition Alarm Timing Figure 7 Start-up Region Alarm Output (LOR + LOL) LOR (Internal Signal) 4 LOL (Internal Signal) 2 3 Phase Detector (Internal Signal) 1 1 External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 AlarmTiming Legend Use for all alarm timing diagrams Table 7 19.44 MHz Reference Input Units 8 kHz Reference Input Units < 31.25 sec 31.25 sec > 31.25 sec 125 sec wide range Minimum pulse width = 62.5 sec < 1 sec 1 sec > 1 sec LOR is active when LOL is active Minimum pulse width = 2 sec 1 2 3 4 5 Start-up Region During Start-up, The LOL Alaram will pulse during the few seconds of operation Preliminary Data Sheet #: SG040 Page 8 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Loss of Lock Condition Alarm Timing Figure 8 Alarm Output (LOR + LOL) LOR (Internal Signal) LOL (Internal Signal) 5 Phase Detector (Internal Signal) 1 1 3 3 1 1 1 External Reference (Selected Input A or B) Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 9 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Switch from A to B when both are good signals Figure 9 Ref A Ref B Alarm LOL portion of Alarm is Blanked 0.5 sec Sel A/B New Reference Qualification time Switch from A to B when Reference B is lost Figure 10 Ref A Ref B ~8ns Alarm Sel A/B Preliminary Data Sheet #: SG040 Page 10 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Switch from A to B after Reference A is lost Figure 11 Ref A Ref B Alarm 156.25s (8 kHz Ref units) 126s (19.44 MHz Ref units) Alarm Blanked Sel A/B New Reference Qualification time Switch from A to B when A is out of range Figure 12 Ref A Ref B Alarm Alarm Blanked Out of Range In Range Sel A/B New Reference Qualification time Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 11 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Switch from A to B when B is out of range Figure 13 Switch from A to B when B is out of range Ref A Ref B Alarm Alarm Blanked In Range Out of Range SEL A/B New Reference Qualification Time 0.5 sec. Switch from A to B when B is out of range Figure 14 Ref A Ref B Alarm Alarm Blanked Sel A/B New Reference Qualification time Free Run Status Preliminary Data Sheet #: SG040 Page 12 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Recommended PECL Termination Figure 15 3.3 VDC 3.3 VDC 3.3 VDC 130 Vcc Q 82 Vcc D 50 Transmission Line SCGXXXX LVPECL OUTPUT QN GND 130 82 LVPECL INPUT 50 Transmission Line DN GND 3.3 VDC 3.3 VDC Vcc - 2 VDC 50 Vcc Q 50 Transmission Line Vcc D SCGXXXX LVPECL OUTPUT QN GND 50 LVPECL INPUT 50 Transmission Line DN GND Vcc - 2 VDC 3.3 VDC 3.3 VDC 150 Vcc Q 50 Transmission Line 100 Vcc D SCGXXXX LVPECL OUTPUT QN GND 150 LVPECL INPUT DN GND 50 Transmission Line If PECL outputs do not drive a long line (< 0.5"), a single 150 termination resistor to ground may be used for each pin. Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 13 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Tape and Reel Packaging Figure 16 Preliminary Data Sheet #: SG040 Page 14 of 16 Rev: P01 Date: 11/13/03 (c) Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice Solder Profile Figure 17 250 200 Temp (C) 150 100 50 0 1 2 3 4 5 6 7 8 Time(minutes) Recommended Reflow Profile Peak Temp:217C MaxRiseSlope:1.5 C/Sec Time Above150C:100Sec Model Comparison Table Table 8 Model SCG4500 SCG4501 SCG4510 SCG4520 SCG4540 Input Ref Freq 8 kHz/8 kHz 8 kHz/8 kHz 2@1.544 MHz 2@19.44 MHz 2@10 kHz Max Duty Cycle 40/60 40/60 40/60 40/60 40/60 Oscillator Output (Synchronized Output) 77.76 MHz,155.52 MHz,125 MHz 77.76 MHz,155.52 MHz,125 MHz 155.52 MHz 77.76 MHz,155.52 MHz 163.84 MHz Notes Basic Model 32 ppm Pull-in range Other low jitter line card solutions from Connor-Winfield SCG51 Series SCG102A/104A SCG2000 Series SCG2500 Series SCG3000 Series SCG4000 Series SCG4600 Series Single input, jitter filtered with Free Run, 1 CMOS and 3 LVPECL outputs up to 622.08 MHz. Single input, frequency selectable, LVPECL clock smoothers from 77.76 to 777.76 MHz. Single input, jitter filtered with 20ppm Free Run, CMOS outputs from 8 kHz to 125.0 MHz. Dual input, jitter filtered with Free Run, CMOS outputs from 8 kHz to 125.0 MHz. Single input, jitter filtered with Dual LVPECL outputs. Single input, jitter filtered with 20ppm Free Run, LVPECL outputs from 77.76 MHz to 180 MHz. Dual input, jitter filtered with Free Run, 1 CML differential pair output up to 622.08 MHz. Preliminary Data Sheet #: SG040 (c) Copyright 2003 The Connor-Winfield Corp. Page 15 of 16 Rev: P01 Date: 11/13/03 All Rights Reserved Specifications subject to change without notice Revision P00 P01 Revision Date 12/20/01 11/13/03 Note Preliminary Release Updated to V3.01 |
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